Area-efficient VLSI implementation of arithmetic operations in binary finite fields GF( )
نویسنده
چکیده
This paper presents a bit-serial architecture for efficient addition and multiplication in binary finite fields GF( ) using a polynomial basis representation. Moreover, a low-power implementation of the arithmetic circuits and the registers is proposed. The introduced multiplier operates over a wide range of binary finite fields up to an order of . It is detailed that the bit-serial multiplier architecture can be implemented with only 28 gate equivalents, and that it is scalable, highly regular, and very simple to design. For applications which use a fixed (standardized) irreducible polynomial, the silicon area of the multiplier can be significantly reduced by the implementation of a “hard-coded” irreducible polynomial.
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